AnalytischDenker schreef op 3 januari 2020 13:01:
Dat punt van "High Volume Manufacturing" is nog maar zeer de vraag.
Er zijn dus diverse bronnen die bevestigen dat er serieuze issues zijn met de EUV machines, waarvan het belangrijkste issue de lage productiviteit van de EUV machine.1. ASML CTO – Martin van de BrinkProductiviteit:The source power should be also be improved. ASML has demonstrated 500W in the lab, about twice the current number. The current ASML product, the NXE-3400C, is rated at 170 wafers per hour. So that is the status of the first generation of EUV lithography. 250W has been regarded as the minimum for EUV to have a high enough wafer throughput to be acceptable in high-volume manufacturing.Productiekosten chip fabrikanten:One important issue that remains in place is the cost per layer. While the the economics for various levels of multi-patterning has been relatively low, the costs of the current EUV system (NXE EUV 0.33 NA) with single patterning and multi-patterning) is significantly higher. The goal is to be able to move to the next-generation high-NA system (EUV 0.55NA) using just single patterning.www.cdrinfo.com/d7/content/future-euv... 2. Qualcomm Qualcomm Snapdragon 865 flagship fabricated on TSMC 7nm without EUV
Kressin noted that EUV is an upgrade to manufacturing process, but that is not a direct concern of Qualcomm, which gives priority to chip performance, power consumption. He said Qualcomm needs massive production capacity support from mainstream advanced technology.
skystatement.com/qualcomm-snapdragon-...3. TSMCTSMC “not yet happy” with ASML’s EUV scanners
We’re still improving the availability. We have an output power of 250 watts as we expected. Now we can operate the tool with 250 watts consistently. However, there are still some things that we need to improve, so that we can improve the throughput and availability,” Wei said.
……………………………Still, in terms of productivity, there’s still a significant gap with optical lithography. “We’ll be working on that for some time to come,” Van den Brink predicted. Eventually, he wants EUV scanners to be as productive as DUV machines.bits-chips.nl/artikel/tsmc-not-yet-ha...
Dan is er ook nog de issue dat de EUV machines vanaf 5NM blijkbaar tegen bepaalde beperkingen gaat aanlopen.A. Stephen Renwick – NikonNikon-man kritisch over 5 nanometer-EUV lithografie op Advanced Lithography TechXPOT
‘EUV zal moeite hebben om klaar te zijn voor 5 nanometer, beperkt door opbrengstproblemen veroorzaakt door stochastische effecten in de resist’, aldus Renwick. ‘Klaar of niet, het zal wel worden gebruikt.’ Renwick suggereert dat de invoering van multiple-patterning met EUV wellicht nodig is, maar de kosten zou verhogen.www.linkmagazine.nl/18943-2/ B. Mark Lapedus - SemiengineeringAt 5nm, chipmakers might use ASML’s existing 0.33 NA EUV tool, which could require single and/or double patterning EUV. At one point, double patterning EUV appeared to be straightforward. But there are growing concerns that double patterning EUV is too complicated and expensive for many devices. And at 3nm, triple patterning EUV may be necessary, which is not considered viable.semiengineering.com/multi-patterning-...